High performance systems for computers and the like are evolving towards housing the semiconductor integrated-circuit (IC) chips of such systems in high-speed multichip arrays. Many of the IC chips in these high performance systems consume a relatively large amount of power (e.g., 20-125 Watts/cm.sup.2 per chip), and consequently generate relatively large amounts of heat which must be removed. Unfortunately, the heat generation places a practical limit on the housing density of the IC chips. The design of such high-performance systems needs to recognize the problem of the heat generation and provide solutions thereto which can enable high densities of such chips, without significantly compromising the construction of high-speed signal interconnections between chips.
One conventional prior art approach of removing heat from a group of IC chips mounts the back surfaces of the IC chips to a heat conductive base plate and interconnects the IC chips to one another, and to outside signal lines, with wire bond interconnections. Although good heat conduction may be achieved in this manner, the wire bond interconnections provide relatively slow signal propagation, as compared to many other interconnect technologies (e.g., flip-chip solder bump technology) due to relatively large inductance of each wire bond interconnection. As such, this approach is not well suited for dense, high-speed IC packaging.
A second prior art approach, which is more suited to a two-dimensional package, mounts the front surfaces of IC chips to a major supporting substrate with C.sup.4 solder bumps (e.g., flip-chip bonding), with the major substrate providing power to the chips and electrical interconnections between chips. Spring loaded heat sinks mechanically coupled to back surfaces of the IC chips remove heat from the IC chips. While this is an acceptable approach for two-dimensional packaging, it is not well suited for three-dimensional packaging because the spring loaded heat sinks occupy a significant space (volume) above the major substrate which prevents close stacking of several interconnect substrates.
In a third prior art approach, as described in U.S. Pat. No. 5,079,619 to Davidson, the IC chips are housed in planar boards which may be stacked upon one another. Two slots are formed in one of the board's major surfaces, and a heat exchanging plate is positioned within the slots. The heat exchanging plate has a number of interior tubes formed within it which conduct a cooling fluid. Due to the formation of the cooling tubes, the heat exchanging plate is relatively thick, and the planar boards housing the IC chips are consequently thick. This presents a disadvantage for high speed communication of signals between planar boards as such signals must propagate through large vertical distances.
In yet another prior art approach, as described in U.S. Pat. No. 4,450,472 to Tuckerman, et al., a plurality of micro-channels are etched in the back surface of an IC chip, and a cover is attached to the back surface to form a plurality of micro-cooling tubes. The channels are designed to carry a laminar flow of water. Manifolds for receiving and discharging the water coolant are attached at the ends of the micro-cooling tubes. Unfortunately, the construction of the micro-channels and the manifolds is expensive and difficult. Additionally, each chip is housed in a separate package, which is not favorable for high density packaging of IC chips.
To date, prior art cooling systems have not adequately addressed the simultaneous needs for high-speed signal communication in two and three dimensional systems and for efficient cooling of such systems. Accordingly, there is a need for compact, reliable, and highly efficient cooling systems suitable for densely packed, high-speed IC chips, that may manufactured by relatively simple methods.